1. Field of the Invention
The present claimed invention relates to the field of signal buffer circuits. More particularly, the present invention relates to a method and apparatus for increasing input impedance of a buffer circuit.
2. Related Art
High speed digital systems, such as engineering workstations and personal computers, require clock sources that have low jitter and low phase lock loop (PLL) bandwidths. Phase jitter in a system clock reduces the effective clock speed of the workstation or personal computer. More processing performance is gained, for a given clock rate, if the clock signal has less jitter. Therefore, it is advantageous to reduce clock jitter within a clock generation circuit ("clock generator"). Clock generators typically contain PLL circuits.
The PLL circuitry in the clock generator typically contains a voltage controlled oscillator (VCO) that receives a voltage level maintained by filter components. Normally, charging currents and voltage controlled oscillator gains are so high that externally situated filter components are required to achieve the low jitter and bandwidth requirements for clock generator circuits. However, external, e.g., "off-chip," filter components (e.g., capacitors, etc.) increase the overall cost of the digital system in part by making manufacturing more complex, and also increase the physical size of the digital system. Furthermore, off-chip filter components also decrease system reliability by increasing the phase jitter by allowing external noise to be injected into the clock circuit through the PLL filter. Clock jitter is reduced if external elements of the PLL loop filter can be eliminated. To integrate filter components "on-chip," it is necessary to use smaller sized filter components. However, this leads to tighter filter leakage requirements because smaller sized capacitors are more sensitive to changes in current when compared to larger sized capacitors.
It is desired to reduce the effects of leakage current within a PLL circuit because, as discussed above, on-chip filter components are very sensitive to small leakage currents. PLL filters are normally driven by current source circuits and require outputs having a very high impedance. A problem exists in eliminating off-chip filters and placing them on-chip. Namely, reducing the size of the filters (thereby allowing them to be placed on-chip) unfortunately makes these components more sensitive to leakage current which impedes the ideal operation of certain PLL circuits. As a result, it is desired to use buffer circuits that have reduced leakage current to drive differential filters for higher PLL accuracy. At the same time, this circuitry needs to operate from increasingly lower power supply voltages, e.g., to accommodate hand-held and other portable battery operated applications.
Likewise, it is advantageous to sample the filter elements within PLL circuits using high input impedance buffer circuits. The high impedance buffer circuits additionally reduces current leakage across the filter elements.
In operation, a PLL circuit injects current into filter components to establish a voltage at the input of a voltage controlled oscillator circuit in order to alter the frequency of oscillation of the PLL. This current is then ideally held constant over a long period of time (e.g., a "hold time") to maintain the oscillation frequency. During the hold time, the filter elements are electrically sampled by buffer circuits. Leakage across the filter component during the hold time, which exists between PLL correction pulses, will charge the filter component thereby changing its voltage. This changing voltage causes time jitter in the clock frequency because it changes the input voltage to the internal voltage controlled oscillator circuit. Therefore, it is necessary to reduce leakage current associated with the PLL filter component in order to provide an accurate oscillation frequency.
One method for reducing leakage current associated with the PLL filter component is to increase the input impedance of the buffer circuits which sample the voltage across the filter elements, e.g., capacitors and/or resistors in electrical combination. FIG. 1 illustrates one such prior art buffer circuit 10. The buffer circuit has a first stage 14 and a second stage 16.
Both stages act as high impedance voltage followers. The voltage input, Vin, into the first stage is applied to node 5 and the voltage output, Vout, from the first stage is shown at node 26. In the first stage, transistor 18 is an emitter follower transistor while transistor 20 provides level shifting. Filter elements would be coupled to node 5. Current source transistors 22 and 24 provide biasing for transistors 18 and 20. The output node, Vout, is taken at node 26 which is coupled to transistor 20. Transistors 18 and current source 22 are coupled to a power supply, Vcc, 23. Current source transistor 24 is coupled to ground 25. The input impedance of the buffer circuit 10 is a function of the beta value of transistor 18 multiplied by the parallel combination of the parallel output impedance of current source transistors 22 and 24. Unfortunately, however, it has been determined that this input impedance buffer scheme is still not enough to meet the stringent requirements necessary to implement an on-chip filter.
Accordingly, what is needed is a buffer circuit for buffering an input voltage level that has a higher input impedance than that realized by prior art buffer circuits. What is also needed is a buffer circuit having a higher input impedance than realized by the prior art buffer circuits described above that can also effectively operate within a low power supply voltage environment. Such a buffer circuit can advantageously be used within a clock generation circuit to sample the charge on an integrated circuit capacitor of a PLL circuit. The claimed present invention provides these advantageous capabilities.